Additive metallization processes are distinguished from subtractive processes in that metal is selectively applied, usually by electroplating, only in the areas of the integrated circuit desired to be metallized. In substractive processes, most commonly used with aluminum and Al-alloy metallization, the entire area of the substrate is covered, usually by bias-sputtering. Then, the desired circuit interconnect pattern is formed by subsequent removal of portions of the deposited metal. An overview of subtractive metallization is presented in an article by J. L. Vossen, "VLSI Metallization Problems and Trends" in Semiconductor International, pages 91-99, September, 1981. A further discussion of problems encountered in Al-based metallization is included in the text by S. M. Sze, entitled VLSI Technology, pages 361-372 (1983).
Additive metallization, particularly using gold but also using noble metals and copper and silver, has a number of advantages over Al-metallization in providing low-resistance integrated circuit interconnects. Most of these metals are easy to electrodeposit on integrated circuits. All but palladium and platinum provide very low sheet resistance, i.e. no more than doped aluminum. The noble metals all provide corrosion and oxidation resistance. Such metals are much more costly than aluminum. In very small-geometry integrated circuits, however, higher material cost is offset by relatively lower process cost increases than occasioned by scale reductions in Al-metallized circuits, potential for better performance characteristics, and reduced likelihood of electromigration-induced failures. Aluminum also readily oxidizes on any exposed surfaces, which can be a factor in reduction of yields of multiple metallization layer circuits.
An example and advantages of gold metallization techniques are described by D. Summers in "A Process For Two-Layer Gold IC Metallization," in Solid State Technology, pages 137-141, December, 1983. In this article the author identifies a number of problems. One is obtaining adequate dielectric coverage of the sidewalls of the metallization. In additive processes, the metal sidewalls have a slight negative or overhanging taper. This is in contrast to subtractive metallization processes, for example as shown in FIG. 12 on page 363 of VLSI Technology, which provide a positive taper. As metallization spacing is reduced and wall angle becomes more severe, sidewall coverage by line-of-sight deposition techniques is significantly reduced relative to top coverage. The inability to cover the metal sidewalls adequately with dielectric material can produce a defect or cusp extending through the dielectric to the base of the metallization. As described by D. Summers on pages 139-140, abnormal leakage currents can result.
We have discovered that the foregoing problem is worsened when a device made according to the D. Summers' process is annealed. As annealing temperatures approach the melting point of the metal, the metallization structures soften and gradually deform. In additive metallization processes, such deformation causes the metal sidewalls to bulge outward, in a bread-loaf-like overhang, increasing cusp defects. Bulging by as much as 200 nanometers (nm) has been observed. Such deformation can occur in low melting point metals, e.g., gold, silver and copper, even at a relatively low annealing temperature. Deformation can also occur with aluminum metallization but initially having a positive taper makes the problem less severe. Corrosion-resistant metals like gold are not, however, amenable to the subtractive metallization processes which yield a positive taper. Summers suggests several other possible techniques for reducing leakage, but none of them deal with breadloafing.
Accordingly, a need remains for a satisfactory additive metallization process, particularly one suitable for gold-metallization in very small-geometry, dense integrated circuits.